Evaluation Method of CMOS Devices Reliability at Cryogenic Temperature Based on SSI Model

Xueqi Yang, Guicui Fu, Bo Wan, Yutai Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

With the development of deep-space exploration, electronic components and integrated circuits in the spacecraft must face the harsh environment in deep space, including cryogenic temperature. For CMOS devices, cryogenic temperature may cause issues in reliability. To qualify the normal application of CMOS devices, an evaluation method of CMOS devices at cryogenic temperature based on stress-strength interference theory was proposed. Moreover, according to the method, stress-strength interference models were built to calculate the failure probability of SN74AHC14 CMOS Inverters at cryogenic temperature.

Original languageEnglish
Title of host publicationProceedings of 2020 International Conference on Sensing, Diagnostics, Prognostics, and Control, SDPC 2020
EditorsYong Qin, Ming J. Zuo, Xiaojian Yi, Limin Jia, Dejan Gjorgjevikj
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages87-92
Number of pages6
ISBN (Electronic)9781728170503
DOIs
StatePublished - 5 Aug 2020
Externally publishedYes
Event4th International Conference on Sensing, Diagnostics, Prognostics, and Control, SDPC 2020 - Virtual, Beijing, China
Duration: 5 Aug 20207 Aug 2020

Publication series

NameProceedings of 2020 International Conference on Sensing, Diagnostics, Prognostics, and Control, SDPC 2020

Conference

Conference4th International Conference on Sensing, Diagnostics, Prognostics, and Control, SDPC 2020
Country/TerritoryChina
CityVirtual, Beijing
Period5/08/207/08/20

Keywords

  • CMOS
  • evaluation
  • low temperature
  • reliability

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