Design of Anti-Interference RF Chip in Satellite Navigation Receiver

In this paper, an anti-interference RF chip architecture of satellite navigation receiver is proposed based on the low-IF architecture. Weak satellite navigation signals are very vulnerable to electromagnetic interference. As a key component of satellite navigation receiver, the RF receiver circuit largely determines the performance of the whole receiver in terms of anti-interference. In order to meet the requirements of compatibility and low power consumption, the design scheme of double-channel, multi-frequency and various working modes according to interference intensity is proposed. A complete anti-interference RF chip is implemented in a 180-nm standard CMOS process with a 3300 \mu \mathrm{m}\times 3000 \mu \mathrm{m} (9.9mm2) size. The proposed method and circuit are tested and verified. In normal navigation mode, the power consumption of the chip is only 111mW. In anti-interference mode, the anti-interference performance of the satellite navigation receiver can reach 87dB jamming-To-signal ratio(JSR). The test result shows that the chip can meet the requirements of anti-interference satellite navigation receiver.