TY - GEN
T1 - Design of Anti-Interference RF Chip in Satellite Navigation Receiver
AU - Yin, Yue
AU - Fan, Jianfeng
AU - Qi, Haobo
AU - Zhou, Shigang
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In this paper, an anti-interference RF chip architecture of satellite navigation receiver is proposed based on the low-IF architecture. Weak satellite navigation signals are very vulnerable to electromagnetic interference. As a key component of satellite navigation receiver, the RF receiver circuit largely determines the performance of the whole receiver in terms of anti-interference. In order to meet the requirements of compatibility and low power consumption, the design scheme of double-channel, multi-frequency and various working modes according to interference intensity is proposed. A complete anti-interference RF chip is implemented in a 180-nm standard CMOS process with a 3300 \mu \mathrm{m}\times 3000 \mu \mathrm{m} (9.9mm2) size. The proposed method and circuit are tested and verified. In normal navigation mode, the power consumption of the chip is only 111mW. In anti-interference mode, the anti-interference performance of the satellite navigation receiver can reach 87dB jamming-To-signal ratio(JSR). The test result shows that the chip can meet the requirements of anti-interference satellite navigation receiver.
AB - In this paper, an anti-interference RF chip architecture of satellite navigation receiver is proposed based on the low-IF architecture. Weak satellite navigation signals are very vulnerable to electromagnetic interference. As a key component of satellite navigation receiver, the RF receiver circuit largely determines the performance of the whole receiver in terms of anti-interference. In order to meet the requirements of compatibility and low power consumption, the design scheme of double-channel, multi-frequency and various working modes according to interference intensity is proposed. A complete anti-interference RF chip is implemented in a 180-nm standard CMOS process with a 3300 \mu \mathrm{m}\times 3000 \mu \mathrm{m} (9.9mm2) size. The proposed method and circuit are tested and verified. In normal navigation mode, the power consumption of the chip is only 111mW. In anti-interference mode, the anti-interference performance of the satellite navigation receiver can reach 87dB jamming-To-signal ratio(JSR). The test result shows that the chip can meet the requirements of anti-interference satellite navigation receiver.
KW - anti-interference RF chip
KW - low-IF architecture
KW - RF receiver circuit
KW - satellite navigation
UR - http://www.scopus.com/inward/record.url?scp=85124141166&partnerID=8YFLogxK
U2 - 10.1109/IMWS-AMP53428.2021.9643943
DO - 10.1109/IMWS-AMP53428.2021.9643943
M3 - 会议稿件
AN - SCOPUS:85124141166
T3 - 2021 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications, IMWS-AMP 2021
SP - 358
EP - 360
BT - 2021 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications, IMWS-AMP 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications, IMWS-AMP 2021
Y2 - 15 November 2021 through 17 November 2021
ER -