An efficient high-speed real-time partially reconfigurable platform for evolvable hardware

Aim. The introduction of the full paper reviews a number of relevant papers in the open literature, points out what we believe to be their shortcomings and then proposes what we believe to be an efficient partially reconfigurable platform design, which is explained in sections 1,2 and 3. Their core consists of: (1) we use the system on programmable chip (SOPC) to design the evolvable hardware platform which can enhance the reconfiguration ability of commercial FPGA (field programmable gate array) and support high-speed real-time partial reconfiguration; the reconfiguration speed measured is 1600 Mbps; (2) the design of the reconfiguration granularity of the evolvable hardware platform is flexible, thus overcoming the shortcomings that the reconfiguration granularity of commercial FPGA is too small and that the chromosomes of an evolvable circuit are too long and that the search time of the genetic algorithm is too long; (3) we improve the existing genetic algorithm. With the improved genetic algorithm, section 4 implements our evolvable platform on Altera's EP2C50 FPGA chip and performs experiments on the evolution of four types of reconfigurable circuit; the experimental results, presented in Fig.3, and their analysis show preliminarily that for a population size of 100, our evolvable hardware uses only about 0.07 seconds to evolve one generation of population, thus being efficient for circuit evolution.