New prefetch technique design for L2 cache

Wenxin Qu; Xiaoya Fan; Ying Hu; Yong Xia; Fuyuan Hu

doi:10.1109/TENCON.2006.344002

New prefetch technique design for L2 cache

Wenxin Qu, Xiaoya Fan, Ying Hu, Yong Xia, Fuyuan Hu

School of Computer Science

Northwestern Polytechnical University Xian

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The memory system remains a major performance bottleneck in the modern and future architectures. Cache Unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (Timing Stride Prefetching, TSP), which is suitable for prefetching at the LZ cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (Instructions Per Cycle) is increased by 8.3%.

Original language	English
Title of host publication	2006 IEEE Region 10 Conference, TENCON 2006
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	1424405491, 9781424405497
DOIs	https://doi.org/10.1109/TENCON.2006.344002
State	Published - 2006
Event	2006 IEEE Region 10 Conference, TENCON 2006 - Hong Kong, China Duration: 14 Nov 2006 → 17 Nov 2006

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON
ISSN (Print)	2159-3442
ISSN (Electronic)	2159-3450

Conference

Conference	2006 IEEE Region 10 Conference, TENCON 2006
Country/Territory	China
City	Hong Kong
Period	14/11/06 → 17/11/06

Access to Document

10.1109/TENCON.2006.344002

Cite this

@inproceedings{141f304c088448188a735acf32097c20,

title = "New prefetch technique design for L2 cache",

abstract = "The memory system remains a major performance bottleneck in the modern and future architectures. Cache Unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (Timing Stride Prefetching, TSP), which is suitable for prefetching at the LZ cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (Instructions Per Cycle) is increased by 8.3%.",

author = "Wenxin Qu and Xiaoya Fan and Ying Hu and Yong Xia and Fuyuan Hu",

year = "2006",

doi = "10.1109/TENCON.2006.344002",

language = "英语",

isbn = "1424405491",

series = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2006 IEEE Region 10 Conference, TENCON 2006",

note = "2006 IEEE Region 10 Conference, TENCON 2006 ; Conference date: 14-11-2006 Through 17-11-2006",

}

Qu, W, Fan, X, Hu, Y, Xia, Y & Hu, F 2006, New prefetch technique design for L2 cache. in 2006 IEEE Region 10 Conference, TENCON 2006., 4142308, IEEE Region 10 Annual International Conference, Proceedings/TENCON, Institute of Electrical and Electronics Engineers Inc., 2006 IEEE Region 10 Conference, TENCON 2006, Hong Kong, China, 14/11/06. https://doi.org/10.1109/TENCON.2006.344002

New prefetch technique design for L2 cache. / Qu, Wenxin; Fan, Xiaoya; Hu, Ying et al.
2006 IEEE Region 10 Conference, TENCON 2006. Institute of Electrical and Electronics Engineers Inc., 2006. 4142308 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hu, Fuyuan

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N2 - The memory system remains a major performance bottleneck in the modern and future architectures. Cache Unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (Timing Stride Prefetching, TSP), which is suitable for prefetching at the LZ cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (Instructions Per Cycle) is increased by 8.3%.

AB - The memory system remains a major performance bottleneck in the modern and future architectures. Cache Unit design and optimization have become an increasingly important factor in determining the overall system performance. This dissertation focuses on the research of the prefetching technique of L2 Cache. A new prefetch technique (Timing Stride Prefetching, TSP), which is suitable for prefetching at the LZ cache, is proposed. Compared with traditional stride prefetch technique, the TSP's timeliness is improved and its IPC (Instructions Per Cycle) is increased by 8.3%.

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SN - 9781424405497

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE Region 10 Conference, TENCON 2006

Y2 - 14 November 2006 through 17 November 2006

ER -

New prefetch technique design for L2 cache

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