@inproceedings{2721715818174db09b36b3a72f1a182c,
title = "Memory compact high-speed QC-LDPC decoder",
abstract = "In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We demonstrate significant benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. It shows that our decoder can operate at a maximum frequency of 250 MHz after place and route and achieve a throughput up to 2 Gbps at 14 iterations.",
keywords = "CCSDS, decoder, FP-GA, High-Speed, memory, QC-LDPC",
author = "Tianjiao Xie and Bo Li and Mao Yang and Zhongjiang Yan",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 7th IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2017 ; Conference date: 22-10-2017 Through 25-10-2017",
year = "2017",
month = dec,
day = "29",
doi = "10.1109/ICSPCC.2017.8242475",
language = "英语",
series = "2017 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--5",
booktitle = "2017 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2017",
}