IP core design and simulation for spacecraft attitude determination algorithm

In order to improve the calculating speed of attitude determination algorithm, the IP (Intellectual Property) core of attitude determination algorithm based on FPGA (Field Programmable Gate Array) was designed on the analysis of deterministic attitude determination algorithm in existence. In each module of the program, the state machine was adopted to complete the computation of attitude determination by controlling RAM (Random Access Memory) to read or write data to different arithmetic units. With pipeline techniques, the program was modeled and synthesized in Quartus II, and finally it was simulated in the hardware simulation tool ModelSim. The attitude determination algorithm was implemented in NIOS II with software in the meantime. The result of simulation shows that, the calculation period of the hardware is about 20μs after finishing the first attitude determination, which is much quicker than the software's runtime, 500μs.