Hardware Design and Simulation Test for NAND Flash Controller

Jiquan Ran; Lin Guo; Sangang Zhang; Jiezhong Ma; Zhengjun Zhai; Yangming Guo

Hardware Design and Simulation Test for NAND Flash Controller

Jiquan Ran, Lin Guo, Sangang Zhang, Jiezhong Ma, Zhengjun Zhai, Yangming Guo

School of Cybersecurity

Research output: Contribution to journal › Article › peer-review

Abstract

The performance of NAND Flash memory chips is largely affected by the NAND Flash controller. So the NAND Flash storage structure and interfaces are analyzed in this paper, then the functions of the controller are designed and each command transition in execution is described. All the operations, such as read and write, are executed via simulation to test the controller's functions. The results show that the controller works well and it meets with the design requirements.

Original language	English
Pages (from-to)	304-309
Number of pages	6
Journal	Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University
Volume	35
Issue number	2
State	Published - 1 Apr 2017

Keywords

Controllers
Interface
NAND Flash
Storage structure

Cite this

@article{0852dc409336459599c4f32f20e2710d,

title = "Hardware Design and Simulation Test for NAND Flash Controller",

abstract = "The performance of NAND Flash memory chips is largely affected by the NAND Flash controller. So the NAND Flash storage structure and interfaces are analyzed in this paper, then the functions of the controller are designed and each command transition in execution is described. All the operations, such as read and write, are executed via simulation to test the controller's functions. The results show that the controller works well and it meets with the design requirements.",

keywords = "Controllers, Interface, NAND Flash, Storage structure",

author = "Jiquan Ran and Lin Guo and Sangang Zhang and Jiezhong Ma and Zhengjun Zhai and Yangming Guo",

year = "2017",

month = apr,

day = "1",

language = "英语",

volume = "35",

pages = "304--309",

journal = "Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University",

issn = "1000-2758",

publisher = "Northwestern Polytechnical University",

number = "2",

}

TY - JOUR

T1 - Hardware Design and Simulation Test for NAND Flash Controller

AU - Ran, Jiquan

AU - Guo, Lin

AU - Zhang, Sangang

AU - Ma, Jiezhong

AU - Zhai, Zhengjun

AU - Guo, Yangming

PY - 2017/4/1

Y1 - 2017/4/1

N2 - The performance of NAND Flash memory chips is largely affected by the NAND Flash controller. So the NAND Flash storage structure and interfaces are analyzed in this paper, then the functions of the controller are designed and each command transition in execution is described. All the operations, such as read and write, are executed via simulation to test the controller's functions. The results show that the controller works well and it meets with the design requirements.

AB - The performance of NAND Flash memory chips is largely affected by the NAND Flash controller. So the NAND Flash storage structure and interfaces are analyzed in this paper, then the functions of the controller are designed and each command transition in execution is described. All the operations, such as read and write, are executed via simulation to test the controller's functions. The results show that the controller works well and it meets with the design requirements.

KW - Controllers

KW - Interface

KW - NAND Flash

KW - Storage structure

UR - http://www.scopus.com/inward/record.url?scp=85019711093&partnerID=8YFLogxK

M3 - 文章

AN - SCOPUS:85019711093

SN - 1000-2758

VL - 35

SP - 304

EP - 309

JO - Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

JF - Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

IS - 2

ER -

Hardware Design and Simulation Test for NAND Flash Controller

Abstract

Keywords

Other files and links

Fingerprint

Cite this