Recognizing geometric path from polygon-based integrated circuit layout

Yuan Zhaohui, Sun Shilei, Wang Gaofeng

科研成果: 书/报告/会议事项章节会议稿件同行评审

1 引用 (Scopus)

摘要

As the continual decrease of the feature size, The parasitic inductance and capacitance effect play important role in IC design and verification. Previous works on layout extraction mainly concentrated on how to find out the type of devices and connections between them, few works has addressed the information of centerlines and widths of IC interconnects in a polygon-based VLSI layout, which are required in inductance calculation and other applications. In this paper, an efficient scheme for the centerline-based path recognition from an IC mask layout is presented. Unlike the division-based methods, a tree-traverse-based approach is proposed. This new scheme can be realized as a reverse procedure of the layout generation from wire routing trees. Moreover, this scheme can handle complex all-angle wires. Experimental results show that this scheme has nearly linear computational complexity yet generates precise results.

源语言英语
主期刊名Proceedings of The 5th IEEE International Symposium on Embedded Computing, SEC 2008
31-36
页数6
DOI
出版状态已出版 - 2008
已对外发布
活动The 5th IEEE International Symposium on Embedded Computing, SEC 2008 - Beijing, 中国
期限: 6 10月 20088 10月 2008

出版系列

姓名Proceedings of The 5th IEEE International Symposium on Embedded Computing, SEC 2008

会议

会议The 5th IEEE International Symposium on Embedded Computing, SEC 2008
国家/地区中国
Beijing
时期6/10/088/10/08

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