TY - JOUR
T1 - Improvement of memory characteristics for an organic charge trapping memory by introduction of PS tunneling layer
AU - Zhang, Peng
AU - Yi, Mingdong
AU - Huang, Liya
AU - Shi, Wei
AU - Zhu, Jintao
AU - Huang, Wei
N1 - Publisher Copyright:
© 2020 Elsevier B.V.
PY - 2020/12
Y1 - 2020/12
N2 - An organic charge trapping memory was fabricated employing (3-aminopropyl) triethoxysilane (APTES) self-assembled monolayer (SAM) as the charge trapping layer, and pentacene as the active layer. In the initial trial, APTES SAM is directly in contact with the active layer, which shows inferior memory characteristics exhibiting as small memory window, low reading currents ratio in WRER test, and short retention time. By introducing a thin Polystyrene (PS) tunneling layer between APTES SAM and active layer, all aspects of memory characteristics have been ameliorated, including enlarged memory window, much increased reading currents ratio in WRER test, and much longer retention time. Interestingly, the programming efficiency is not affected by the introduction of the PS tunneling layer, showing a short programming time of less than 1 μs. However, with further increase of PS tunneling layer thickness, the reading current ratio in WRER test and the programming efficiency is slightly decreased. In addition, the retention time is also slightly shorter in terms of thicker PS tunneling layer. Nevertheless, the comprehensive improvement of the memory characteristics by introducing PS tunneling layer enables the potential applications of a nonvolatile memory device.
AB - An organic charge trapping memory was fabricated employing (3-aminopropyl) triethoxysilane (APTES) self-assembled monolayer (SAM) as the charge trapping layer, and pentacene as the active layer. In the initial trial, APTES SAM is directly in contact with the active layer, which shows inferior memory characteristics exhibiting as small memory window, low reading currents ratio in WRER test, and short retention time. By introducing a thin Polystyrene (PS) tunneling layer between APTES SAM and active layer, all aspects of memory characteristics have been ameliorated, including enlarged memory window, much increased reading currents ratio in WRER test, and much longer retention time. Interestingly, the programming efficiency is not affected by the introduction of the PS tunneling layer, showing a short programming time of less than 1 μs. However, with further increase of PS tunneling layer thickness, the reading current ratio in WRER test and the programming efficiency is slightly decreased. In addition, the retention time is also slightly shorter in terms of thicker PS tunneling layer. Nevertheless, the comprehensive improvement of the memory characteristics by introducing PS tunneling layer enables the potential applications of a nonvolatile memory device.
KW - APTES SAM
KW - Charge trapping memory
KW - Organic thin film transistor
KW - PS tunneling Layer
UR - http://www.scopus.com/inward/record.url?scp=85091783430&partnerID=8YFLogxK
U2 - 10.1016/j.orgel.2020.105967
DO - 10.1016/j.orgel.2020.105967
M3 - 文章
AN - SCOPUS:85091783430
SN - 1566-1199
VL - 87
JO - Organic Electronics
JF - Organic Electronics
M1 - 105967
ER -