Exploring modeling and testing approaches for three-dimensional integrated thermal resistance of chiplets

The advent of three-dimensional stacked chips has significantly enhanced overall performance but introduced challenges in thermal analysis. To ensure the reliable operation of stacked chips and improve the design efficiency of heat sinks, a comprehensive exploration of thermal management issues, the formulation of practical thermal design principles, and the development of a foundational heat transfer analysis model are imperative. In this study, a three-dimensional stacked module is modeled using FloTHERM finite element simulation technology, and its temperature profile is subsequently simulated. The thermal resistance value of the module's shell is calculated to be 37.25 °C W⁻¹. Subsequently, utilizing the instantaneous state dual interface method, the junction-to-case thermal resistance of the module is experimentally measured using T3ster equipment. Two identical modules are tested, revealing a junction-to-case resistance value of 39.45 °C W⁻¹ for module No. 1 and 40.50 °C W⁻¹ for module No. 2—both approximately 40 °C W⁻¹, thereby validating the accuracy and repeatability of the tests. A comparative analysis between the simulated and experimental thermal resistance values indicates an error of approximately − 5.5% for module 1 and − 8.0% for module 2. Further analysis suggests potential sources of error, such as thermal conductivity of the plastic packaging material and hot spot distribution. The paper concludes with simulation-based analyses of plastic packaging material thermal conductivity and hot spot distribution, offering insights for refining the simulation model. This study verifies the correctness of the results obtained by using finite element analysis to build a model for thermal simulation analysis. It has reference value for the thermal simulation analysis and thermal resistance test method of 3D integrated package module.