@inproceedings{1cd5d9f647ca45ef82d24961da0b72cc,
title = "Efficient architecture and protocol for image acquisition",
abstract = "Because of the advantages of high sampling rate, high-speed image acquisition system is widely used in military, sports, biological and other fields. Unfortunately, just due to its high frame rate, the design risk and design cycle are greatly increased, and the back end image processing is still a challenging problem. In order to solve this problem, an image acquisition system architecture and protocol is proposed in this paper, which divides the image acquisition system into control plane and processing plane. The processing plane is divided into sensor independent layer, cache layer, processing layer and application layer. These layers are physically connected by AXI bus, and the logical relationship between them is as small as possible. Our proposed architecture and protocol effectively reduces the design complexity and design risk, also the design efficiency is greatly improved.",
keywords = "Architecture and protocol, AXI bus, Design efficiency, Design risk, FPGA, Image acquisition",
author = "Yanlang Hu and Ying Li and Yanning Zhang and Quan Zhou and Juanni Liu and Jiayuan Wei",
note = "Publisher Copyright: {\textcopyright} 2019 SPIE.; 11th International Conference on Graphics and Image Processing, ICGIP 2019 ; Conference date: 12-10-2019 Through 14-10-2019",
year = "2020",
doi = "10.1117/12.2557602",
language = "英语",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
publisher = "SPIE",
editor = "Zhigeng Pan and Xun Wang",
booktitle = "Eleventh International Conference on Graphics and Image Processing, ICGIP 2019",
}