A 1.7 ps equivalent bin size and 4.2 ps RMS FPGA TDC based on multichain measurements averaging method

A high precision and high resolution time-to-digital converter (TDC) based on multichain measurements averaging method is implemented in a 40 nm fabrication process Virtex-6 FPGA. The results of the detailed theoretical analysis and the simulation with the MATLAB tool based on a complete TDC module show that the resolution limitation determined by the intrinsic cell delay of plain tapped-delay chain can be overcame, which results in an improvement on both resolution and precision without increasing the dead time. The test results agree with the simulation results quite well. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the number of the chains is M), and each chain is just a plain TDC and generates a timestamp for a hit signal. Therefore, M timestamps should be obtained in total, which, after averaging, give the final timestamp. A TDC with 1.7 ps equivalent bin size, 1.5 ps averaged bin size and 4.2 ps RMS has been implemented with M being 16, which performs much better than the plain TDC constructed of a single tapped delay chain having 42.3 ps equivalent bin size, 24.0 ps averaged bin size resolution and 13.2 ps RMS precision. The comparisons of equivalent bin size and averaged bin size show that the nonlinearity is improved with a larger M. Due to the real time integral nonlinearity (INL) calibration and averaging calculation, the multichain TDC is almost insensitive to the process voltage and temperature (PVT) variations.