Parallel implementation of the auxiliary power system model of the electric locomotive for hardware-in-the-loop simulation

Hardware-in-the-loop simulation (HiLs) is an enabling technology for analysing and testing the control unit of highpower electronic system. However, the main difficulty remains in the design of a HiLs platform for a control unit with a complex electronic system. With the attempt to improve this issue, this study presents the HiLs setup utilising the dSPACE simulator under the background of the auxiliary power system of the electric locomotive. A massive parallel implementation approach for modelling the auxiliary power system is proposed for the implementation on field programmable gate arrays (FPGAs). The proposed method exploits the large response time of the auxiliary model to: (i) decouple the complex system into independent sub-systems, (ii) partition the AC machine model solution from the rest power electronic system using the FPGA/CPU co-mix structure, and (iii) adopt nanoseconds range simulation time step. The whole HIL system can be used to evaluate both the hardware and software performance of the physical auxiliary control unit. The real time simulation results under steady-state and transient conditions demonstrate modelling accuracy and provide detailed insight into the development of this electrical powertrain.