TY - GEN
T1 - Numerical Simulation of Impact Response of Board-Level Packaging Structure
AU - Long, Xu
AU - Hu, Yuntao
AU - Su, Tianxiong
AU - Chang, Chao
N1 - Publisher Copyright:
© 2024, The Author(s), under exclusive license to Springer Nature Switzerland AG.
PY - 2024
Y1 - 2024
N2 - Board-level drop responses are critical to evaluate the mechanical reliability of solder joints to serve as electrical and mechanical connections in electronic devices to resist failure due to drop impact. In this paper, by applying the elastoplastic constitutive models of solder materials and polymer materials in the BGA packaging structure, drop impact simulations of board-level packaging structure are performed according to the new version of JEDEC revised in 2016, JESD22-B111A for the drop test standard for portable electronic products. Particularly, the Input-G method is adopted, using a semi-sinusoidal acceleration pulse load with a peak of 1500G and a pulse time of 0.5 ms. The overall finite element model establishes a 1/4 model thanks to the symmetry of the board-level packaging structure. According to the simulation results, we explored the failure mode of the solder joint and polymer layer. At the same time, the mechanical reliability of different solder joints in the packaging structure is also discussed according to the production requirements. The results show that the solder joint far away from the center point of the PCB board is subjected to the greatest stress, which is the most vulnerable solder joint. It is found that the stress component in the vertical direction plays a leading role, which can be treated as the peeling stress. Peeling stress is the major reason to cause the crack occurrence and propagation in the solder joint, which is the main failure mode for solder joint. Under the same load, three BGA models with different solder joint distributions are compared.
AB - Board-level drop responses are critical to evaluate the mechanical reliability of solder joints to serve as electrical and mechanical connections in electronic devices to resist failure due to drop impact. In this paper, by applying the elastoplastic constitutive models of solder materials and polymer materials in the BGA packaging structure, drop impact simulations of board-level packaging structure are performed according to the new version of JEDEC revised in 2016, JESD22-B111A for the drop test standard for portable electronic products. Particularly, the Input-G method is adopted, using a semi-sinusoidal acceleration pulse load with a peak of 1500G and a pulse time of 0.5 ms. The overall finite element model establishes a 1/4 model thanks to the symmetry of the board-level packaging structure. According to the simulation results, we explored the failure mode of the solder joint and polymer layer. At the same time, the mechanical reliability of different solder joints in the packaging structure is also discussed according to the production requirements. The results show that the solder joint far away from the center point of the PCB board is subjected to the greatest stress, which is the most vulnerable solder joint. It is found that the stress component in the vertical direction plays a leading role, which can be treated as the peeling stress. Peeling stress is the major reason to cause the crack occurrence and propagation in the solder joint, which is the main failure mode for solder joint. Under the same load, three BGA models with different solder joint distributions are compared.
KW - Board-level packaging structure
KW - Drop impact
KW - Dynamic response
KW - Finite element method
KW - Input-G method
UR - http://www.scopus.com/inward/record.url?scp=85180622846&partnerID=8YFLogxK
U2 - 10.1007/978-3-031-42987-3_101
DO - 10.1007/978-3-031-42987-3_101
M3 - 会议稿件
AN - SCOPUS:85180622846
SN - 9783031429866
T3 - Mechanisms and Machine Science
SP - 1443
EP - 1453
BT - Computational and Experimental Simulations in Engineering - Proceedings of ICCES 2023—Volume 2
A2 - Li, Shaofan
PB - Springer Science and Business Media B.V.
T2 - 29th International Conference on Computational and Experimental Engineering and Sciences, ICCES 2023
Y2 - 26 May 2023 through 29 May 2023
ER -