TY - GEN
T1 - Mutual effect of instruction layout optimization and instruction memory hierarchy
AU - Wang, Yu Ying
AU - Zhou, Xing She
PY - 2007
Y1 - 2007
N2 - Instruction layout optimization can efficiently improve the performance of instruction cache by dramatically reducing the instruction fetch miss rate. Traditional instruction layout optimization methods usually do not consider tuning the hardware architecture of the instruction cache in the optimizing process. Therefore, they trend to result in local-optimal solutions. This paper studies the mutual effect of the instruction layout optimization and the instruction memory hierarchy. We built a framework to perform the instruction layout optimizations by profiling the call graph and reordering the instructions at the procedure level. Then, the original procedure and instruction layout optimized one are run on platforms with different cache hierarchy, and the cache miss rates are compared. Experimental results show that the instruction cache configuration greatly influences the benefit of instruction layout optimization, and the performance of the instruction cache could be potentially improved by jointly considering them together.
AB - Instruction layout optimization can efficiently improve the performance of instruction cache by dramatically reducing the instruction fetch miss rate. Traditional instruction layout optimization methods usually do not consider tuning the hardware architecture of the instruction cache in the optimizing process. Therefore, they trend to result in local-optimal solutions. This paper studies the mutual effect of the instruction layout optimization and the instruction memory hierarchy. We built a framework to perform the instruction layout optimizations by profiling the call graph and reordering the instructions at the procedure level. Then, the original procedure and instruction layout optimized one are run on platforms with different cache hierarchy, and the cache miss rates are compared. Experimental results show that the instruction cache configuration greatly influences the benefit of instruction layout optimization, and the performance of the instruction cache could be potentially improved by jointly considering them together.
KW - Cache memory hierarchy
KW - Instruction cache miss rate
KW - Instruction layout optimization
UR - http://www.scopus.com/inward/record.url?scp=47749140388&partnerID=8YFLogxK
U2 - 10.1109/ICPPW.2007.57
DO - 10.1109/ICPPW.2007.57
M3 - 会议稿件
AN - SCOPUS:47749140388
SN - 0769529348
SN - 9780769529349
T3 - Proceedings of the International Conference on Parallel Processing Workshops
BT - 2007 International Conference on Parallel Processing Workshops, ICPPW
T2 - 2007 International Conference on Parallel Processing Workshops, ICPPW 2007
Y2 - 10 September 2007 through 14 September 2007
ER -