FPGA testing points optimization method based on important analysis

Guochang Zhou, Xiang Gao, Xiaoling Lai, Qi Zhu, Ting Ju, Yangming Guo, Hao Wu, Qiang Zhi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

From the space and time dimension, the FPGA circuit is devised some levels with 'computing unit + memory/register' via analyzing the characteristics of the FPGA circuit. Combined with the location importance, the connection degree among the nodes and their own soft error probability, an importance analysis model is proposed. And then the testing points are optimized based on the importance of each node using the proposed importance analysis model. The test results indicate that the method is a feasible optimization method.

Original languageEnglish
Title of host publicationProceedings of 2016 Prognostics and System Health Management Conference, PHM-Chengdu 2016
EditorsQiang Miao, Zhaojun Li, Ming J. Zuo, Liudong Xing, Zhigang Tian
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509027781
DOIs
StatePublished - 16 Jan 2017
Event7th IEEE Prognostics and System Health Management Conference, PHM-Chengdu 2016 - Chengdu, Sichuan, China
Duration: 19 Oct 201621 Oct 2016

Publication series

NameProceedings of 2016 Prognostics and System Health Management Conference, PHM-Chengdu 2016

Conference

Conference7th IEEE Prognostics and System Health Management Conference, PHM-Chengdu 2016
Country/TerritoryChina
CityChengdu, Sichuan
Period19/10/1621/10/16

Keywords

  • FPGA
  • Important analysis
  • Optimization
  • Soft error of single event effect
  • Testing points

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