Exploring good cache architecture

We aim to explore a cache architecture whose hit ratio is almost as high as the available best but whose power consumption is low and whose hardware is reduced to a minimum. Section 1 of the full paper discusses, with the help of Figs. 1, 2 and 3, the design of the cache architecture we explored. Section 2 designs the fault tolerance of cache architecture. Finally we purposefully perform fault injection to test the reliability of the cache architecture. The test results, given in Table 2, show preliminarily that the cache architecture designed by us does realize: (1) that the hit ratio of our cache architecture is 0.881; (2) that its fault detection coverage is obviously higher than the fully-associative cache architecture.