Advancing Mapping Strategies and Circuit Optimization for Signed Operations in Compute-in-Memory Architecture

Compute-in-memory (CIM) is a key focus in chip design, with mapping strategies gaining attention. However, many studies overlook the arrangement of significant bits in weights and the influence of the input order of activation bits, which are key aspects of bit-level mapping strategies. While the three existing bit-level mapping strategies have their respective application scenarios and can address the majority of cases through combined use, a major challenge remains: their lack of support for signed computations, which limits their applicability in many practical scenarios. This work improves three existing mapping strategies to support signed weights and activations, optimizing CIM peripheral circuits with minimal overhead. The experimental results show a 68.4% improvement in energy efficiency and 56.2% in speed with a less than 1% area increase on Yolov3-tiny, and a (Formula presented.) and (Formula presented.) boost in energy efficiency using input-side parallel mapping strategy (ISP) and input- and output-side parallel mapping strategy (IOSP) on a single layer. The proposed work has the potential to significantly advance the field of CIM-based neural network accelerators by enabling efficient signed computations and enhancing flexibility, paving the way for broader adoption in real-time and energy-constrained applications.