TY - GEN
T1 - A redundant and integrated avionics for 12U CubeSat
AU - Liu, Guanghui
AU - Zhou, Jun
AU - Guo, Jian
N1 - Publisher Copyright:
© 2017 by the International Astronautical Federation. All rights reserved.
PY - 2017
Y1 - 2017
N2 - In this paper, a redundant and integrated avionics for 12U CubeSat is presented. The main innovation is to propose a method to enhance system reliability and fault tolerance based on the COTS(Commercial Off-The-Shelf) devices, as well as to deal with system recoverability for unknown failures without changing the original system hardware. A multi-node architecture based on COTS devices and standard I2C bus is designed considering low cost, modularization, simplification and high-reliability. In order to avoid the I2C bus stuck issue, a bus recovery technology generating 16 clock pulses on the I2C bus is proposed. The cold redundant strategy is utilized on the devices that have no flight heritage. The OBC employs a heterogeneous complementary dual-processor method. A high-speed processor acts the main processor for the normal command data management and attitude control tasks. A high reliability, low-speed processor works as the backup processor for monitoring and fault-tolerant operations, which can protect the system with minimum running cost when the main processor fails. The proposed avionics has been developed and successfully demonstrated on the world's first 12U CubeSat "Star of AoXiang", which was launched on June 25, 2016. the avionics worked without issues until atmospheric re-entry after 99 days in orbit. The in-orbit results of this avionics are presented in this paper.
AB - In this paper, a redundant and integrated avionics for 12U CubeSat is presented. The main innovation is to propose a method to enhance system reliability and fault tolerance based on the COTS(Commercial Off-The-Shelf) devices, as well as to deal with system recoverability for unknown failures without changing the original system hardware. A multi-node architecture based on COTS devices and standard I2C bus is designed considering low cost, modularization, simplification and high-reliability. In order to avoid the I2C bus stuck issue, a bus recovery technology generating 16 clock pulses on the I2C bus is proposed. The cold redundant strategy is utilized on the devices that have no flight heritage. The OBC employs a heterogeneous complementary dual-processor method. A high-speed processor acts the main processor for the normal command data management and attitude control tasks. A high reliability, low-speed processor works as the backup processor for monitoring and fault-tolerant operations, which can protect the system with minimum running cost when the main processor fails. The proposed avionics has been developed and successfully demonstrated on the world's first 12U CubeSat "Star of AoXiang", which was launched on June 25, 2016. the avionics worked without issues until atmospheric re-entry after 99 days in orbit. The in-orbit results of this avionics are presented in this paper.
KW - 12U CubeSat
KW - I2C bus lockup revcover
KW - Integrated avionics
KW - OBC
KW - Star of AoXiang
UR - http://www.scopus.com/inward/record.url?scp=85051404201&partnerID=8YFLogxK
M3 - 会议稿件
AN - SCOPUS:85051404201
SN - 9781510855373
T3 - Proceedings of the International Astronautical Congress, IAC
SP - 6121
EP - 6127
BT - 68th International Astronautical Congress, IAC 2017
PB - International Astronautical Federation, IAF
T2 - 68th International Astronautical Congress: Unlocking Imagination, Fostering Innovation and Strengthening Security, IAC 2017
Y2 - 25 September 2017 through 29 September 2017
ER -