@inproceedings{848d1022f9ac45c6b929a67f581147b6,
title = "A Novel Circuit and Layout Design of SEU Tolerant SRAM in a 65nm CMOS Process",
abstract = "In order to address the vulnerability of embedded SRAMs to single event soft errors due to high-energy particles in a space radiation environment, this paper proposes a novel circuit d layout design of SEU tolerant SRAM based on a DICE structure. A DICE SRAM design with a depth of 4096 and a bit width of 12 is completed based on a commercial 65nm bulk silicon CMOS process, implemented using 3 layers of metal, with an area only 1.6 times that of a non-DICE SRAM. Circuit and irradiation simulation results illustrate that the SRAM has an access time of less than 2.2ns and a single event upset cross section of 1.74×10-13 cm2/bit at an equivalent LET value of 55.3 MeV/mg/cm2 of particle incidence. The SRAM circuit's performance and resistance to single-particle soft errors can significantly reduce the area, wiring resources and timing overhead associated with hardening the embedded SRAM circuit in radiation hardened ASIC designs.",
keywords = "Circuit level, DICE SRAM, Heavy ions, Layout level, Radiation-hardness, Single event upset",
author = "Xiaoling Lai and Yangming Guo and Jian Zhang and Ting Ju and Qi Zhu and Guochang Zhou",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 18th IEEE Conference on Industrial Electronics and Applications, ICIEA 2023 ; Conference date: 18-08-2023 Through 22-08-2023",
year = "2023",
doi = "10.1109/ICIEA58696.2023.10241793",
language = "英语",
series = "Proceedings of the 18th IEEE Conference on Industrial Electronics and Applications, ICIEA 2023",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "522--526",
editor = "Wenjian Cai and Guilin Yang and Jun Qiu and Tingting Gao and Lijun Jiang and Tianjiang Zheng and Xinli Wang",
booktitle = "Proceedings of the 18th IEEE Conference on Industrial Electronics and Applications, ICIEA 2023",
}