Abstract
A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.
Translated title of the contribution | LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA |
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Original language | Chinese (Traditional) |
Pages (from-to) | 299-307 |
Number of pages | 9 |
Journal | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University |
Volume | 37 |
Issue number | 2 |
DOIs | |
State | Published - 1 Apr 2019 |