Study on the mechanical performance of porous polycrystalline sintered silver interconnects under thermal cycling using a coupled CPFEM-CZM model

With the continuous advancement in the integration and miniaturization of power electronic devices, the mechanical reliability of packaging materials has emerged as a critical factor restricting device performance. Sintered silver, with its low-temperature sintering capability, high melting point, and excellent thermal and electrical conductivity, is widely used in chip interconnection of high-temperature SiC power modules. However, due to the mismatch in the coefficient of thermal expansion between the chip and the substrate, the sintered silver bonding layer is subjected to significant shear stress during thermal cycling. This may lead to interfacial debonding and internal structural degradation, thereby affecting the mechanical performance and long-term reliability of the device. Sintered silver exhibits a distinct porous polycrystalline microstructure, and its mechanical behavior under thermal loading is significantly influenced by grain boundaries and pores. In this study, a finite element model of a porous polycrystalline sintered silver chip interconnect was developed to simulate its mechanical response and interfacial damage evolution under thermal cycling loads, thus providing a theoretical basis for the thermal reliability analysis of power devices. Particularly, the state-of-the-art crystal plasticity finite element method (CPFEM) was developed to investigate the influence of mesoscale features on the macroscopic mechanical properties of materials. It should be noted that the interfacial damage and microcrack propagation in polycrystalline materials cannot be accurately predicted using CPFEM. This limitation has persisted in the recent decade and is effectively addressed in this study by integrating the cohesive zone model (CZM) with CPFEM, enabling a more realistic simulation of interfacial failure mechanisms. Simulation results reveal that thermal expansion mismatch induces significant stress concentration at the copper/ceramic and sintered silver/SiC chip interfaces, marking potential failure initiation zones. The combined effects of grain orientation differences, pore disturbances, and interfacial sliding within the mesoscale features of sintered silver further exacerbate local stress inhomogeneity.