Stress evolution characteristics of packaging structures with embedded piezoresistive sensors under thermal cycling loads

The miniaturization of electronic components and the increasing density of solder joint arrays have made the reliability testing and simulation optimization of packaging devices increasingly challenging. Effectively capturing the stress within packaging structures has become a critical issue that needs to be addressed in the field of advanced packaging. This research focuses on wafer-level chip packaging structures, exploring the internal stress evolution under thermal cycling loads and proposing a methodology that integrates experimental and simulation approaches based on embedded silicon-based piezoresistive sensors. By leveraging these sensors for the first time, real-time monitoring of stress variations across different regions of power modules was achieved, offering precise characterization of cumulative stress behavior during thermal cycling. The results indicate that the gradual accumulation of internal stress is predominantly driven by the inherent plastic deformation and creep properties of solder materials under cyclic thermal conditions. Based on this, a unified creep-plasticity constitutive model coupled with damage was developed and compiled into a UMAT subroutine, which was then incorporated into finite element software for simulation. The simulation results closely matched the experimental data, successfully replicating the stress evolution pattern during thermal cycling. This study not only elucidates the underlying mechanisms of stress evolution in advanced packaging structures but also validates the feasibility of using embedded sensor technology and enhanced simulation models to tackle the challenge of stress measurement, providing a novel approach and technical pathway for the reliability design and optimization of packaging structures.