Designing and implementing a better real-time FFT module with block recursive algorithm

Aim: We propose what we believe to be a better module, which is significantly faster than the FFT(Fast Fourier Transform) software module of TMS320C54x DSP (digital signal processor) Library in real-time performance. The key computing of our FFT module is implemented by the FPGA (field programmable gate array) chip and data inputting to and outputting from the FFT module are controlled by DSP, so it is a tradeoff design of hardware and software. Section 2 gives the block diagram as shown in Fig. 2 showing the four sub-block input data frames. This is what we call the block recursive algorithm, which is real-time and suitable for the implementation of the hardware using the FFT-IP core. Section 3 designs the FFT module in accordance with the six strict requirements for the time sequence control of the FFT-IP core. The diagrams for the time sequence of input data stream loading and output data stream unloading respectively are given in Figs. 3 and 4. Section 3 also gives the block diagram for the implementation of the FFT-IP core. To verify the feal-time performance of the block recursive algorithm, we use an oscilloscope to test several time sequence signals of the FFT module. The test results, given in Figs. 5, 6 and 7, show preliminarily that the speed of the FFT module is about 35 times faster than that obtainable with the software module of TMS320C54x DSP Library.