An improved error detection and correction method for single event upset with clock edge

Based on the clock edge, an improved error detection and correction (EDAC) circuit for single event upset (SEU) is proposed in this paper. The circuit can implement the data error detection and correction through determining whether the data and clock are asynchronous or not. It keeps the advantages and overcomes the shortcomings of the EDAC circuit and it can not only complete detection under clock rising or falling edge but also achieve multi-bit SEU error detection and correction. The simulation results and their analysis show preliminarily that the proposed improved EDAC circuit is indeed better.