TY - JOUR
T1 - An 820uW Low Jitter Digital Injection-Locked PLL Using Differential Multi-Phase Injection and Self-Calibration for Biosensing Applications
AU - Li, Zhen
AU - Zheng, Mingxuan
AU - Yang, Fan
AU - Zhang, Xinyuan
AU - Huang, Jialuo
AU - Zhao, Xiaodong
AU - Cui, Yuanyuan
AU - Zhang, Xunying
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - This paper presents a highly energy-efficient, low-jitter digital injection-locked phase-locked loop (ILPLL) tailored for the 2.4 GHz industrial scientific medical band. The proposed digital injection-locking architecture overcomes the limitations of conventional analog approaches regarding power, area, and robustness, and its incorporated differential multi-phase injection technique simultaneously suppresses jitter and further reduces power consumption. The misaligned injection pulse timing and non-optimized injection pulsewidth are digitally calibrated in background to maintain low power and low jitter across process, voltage, and temperature (PVT) variations. Fabricated in a 28-nm CMOS process, the proposed digital ILPLL achieves 542 fs RMS jitter with -65.8 dBc spur at 2.4 GHz working frequency. It consumes 820 ¼W power from a 0.6 V supply voltage, demonstrating the state-of-the-art energy efficiency along with a competitive jitter. In vitro experiment is conducted in a hospital for clinical trials, where the proposed digital ILPLL integrated into an SoC provides a local oscillator signal for the radio frequency front-end, enabling the system to wirelessly transmit electrocardiogram data in a battery-free manner.
AB - This paper presents a highly energy-efficient, low-jitter digital injection-locked phase-locked loop (ILPLL) tailored for the 2.4 GHz industrial scientific medical band. The proposed digital injection-locking architecture overcomes the limitations of conventional analog approaches regarding power, area, and robustness, and its incorporated differential multi-phase injection technique simultaneously suppresses jitter and further reduces power consumption. The misaligned injection pulse timing and non-optimized injection pulsewidth are digitally calibrated in background to maintain low power and low jitter across process, voltage, and temperature (PVT) variations. Fabricated in a 28-nm CMOS process, the proposed digital ILPLL achieves 542 fs RMS jitter with -65.8 dBc spur at 2.4 GHz working frequency. It consumes 820 ¼W power from a 0.6 V supply voltage, demonstrating the state-of-the-art energy efficiency along with a competitive jitter. In vitro experiment is conducted in a hospital for clinical trials, where the proposed digital ILPLL integrated into an SoC provides a local oscillator signal for the radio frequency front-end, enabling the system to wirelessly transmit electrocardiogram data in a battery-free manner.
KW - Biosensor networks
KW - injection-locked phase-locked loop (ILPLL)
KW - low jitter
KW - low power
KW - optimum injection pulse
KW - ring voltage-controlled oscillator (RVCO)
UR - https://www.scopus.com/pages/publications/105040249307
U2 - 10.1109/TBCAS.2026.3697523
DO - 10.1109/TBCAS.2026.3697523
M3 - 文章
AN - SCOPUS:105040249307
SN - 1932-4545
JO - IEEE Transactions on Biomedical Circuits and Systems
JF - IEEE Transactions on Biomedical Circuits and Systems
ER -