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A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train

  • Chen Liu
  • , Xizheng Guo
  • , Rui Ma
  • , Zhongliang Li
  • , Franck Gechter
  • , Fei Gao
  • Fuel Cell Lab (FR CNRS 3539)
  • Université de technologie de Belfort Montbéliard
  • Beijing Jiaotong University
  • Aix-Marseille Université
  • CNRS

科研成果: 期刊稿件文章同行评审

25 引用 (Scopus)

摘要

Hardware-in-the-loop (HIL) test provides a time saving and safe environment for testing high-power electronic systems. But the main difficulty for the HIL test of power electronic system lies on the modeling of the complex and high-power system. This paper proposes a modeling method of the electrical system of high-speed train. With this method, the HIL test platform using field-programmable gate array boards is built. Besides, in order to meet the computing power requirement of the system modeling, we simulate the whole system using two dSPACE simulators and inside each dSPACE simulator, a multiprocessor system is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit and auxiliary control unit. The HIL results under steady state and transient conditions demonstrate modeling accuracy and provide a detailed insight into its development.

源语言英语
文章编号8444450
页(从-至)912-921
页数10
期刊IEEE Transactions on Transportation Electrification
4
4
DOI
出版状态已出版 - 12月 2018

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