TY - JOUR
T1 - A K-Band Four-Channel Beamformer with Temperature Compensation Based on 65 nm CMOS Process
AU - Wang, Cetian
AU - Liu, Yanning
AU - Liao, Xuejie
AU - Zhang, Fan
AU - Deng, Chun
AU - Liu, Ying
AU - Sun, Wenxu
AU - Guan, He
AU - Zhou, Deyun
N1 - Publisher Copyright:
© 2026 by the authors.
PY - 2026/4
Y1 - 2026/4
N2 - This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm2, the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel.
AB - This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm2, the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel.
KW - 65 nm CMOS
KW - K-band
KW - active phased array
KW - beamformer
KW - root mean square
UR - https://www.scopus.com/pages/publications/105036801830
U2 - 10.3390/mi17040462
DO - 10.3390/mi17040462
M3 - 文章
AN - SCOPUS:105036801830
SN - 2072-666X
VL - 17
JO - Micromachines
JF - Micromachines
IS - 4
M1 - 462
ER -