A 152 fsrms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration

Zhen Li; Yuxiao Zhou; Haijin Zhang; Sen Jia; Xing Quan; Xiaodong Zhao; Yuanyuan Cui; Xunying Zhang

doi:10.1109/ESSERC66193.2025.11214107

A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration

Zhen Li
, Yuxiao Zhou
, Haijin Zhang
, Sen Jia
, Xing Quan
, Xiaodong Zhao
, Yuanyuan Cui
, Xunying Zhang

电子信息学院

Northwestern Polytechnical University Xian
School of Microelectronics, Xidian University

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

This paper introduces an injection-locked phase-locked loop (ILPLL) with multi-phase injection and background self-calibrated. By employing multi-phase injection to enhance injection strength, the noise suppression bandwidth is extended and thus achieving low jitter. Moreover, with injection timing and pulsewidth calibration, the noise suppression bandwidth is further improved, while achieving low spur. The proposed ILPLL is fabricated in a 28-nm CMOS, achieving 152 fs RMS jitter with - 66.5dB cspur and - 247.4dB FoM_jitter at 2.4 GHz working frequency. The total power consumption is 7.8 mW from 0.9 V supply voltage.

源语言	英语
主期刊名	Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
出版商	IEEE Computer Society
页	161-164
页数	4
ISBN（电子版）	9798331525392
DOI	https://doi.org/10.1109/ESSERC66193.2025.11214107
出版状态	已出版 - 2025
活动	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 - Munich, 德国期限: 8 9月 2025 → 11 9月 2025

出版系列

姓名	European Solid-State Circuits Conference
ISSN（印刷版）	1930-8833

会议

会议	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
国家/地区	德国
市	Munich
时期	8/09/25 → 11/09/25

访问文件

10.1109/ESSERC66193.2025.11214107

其它文件与链接

链接到 Scopus 的出版物

引用此

Li, Z., Zhou, Y., Zhang, H., Jia, S., Quan, X., Zhao, X., Cui, Y., & Zhang, X. (2025). A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration. 在 Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 (页码 161-164). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC66193.2025.11214107

@inproceedings{6fc9eba7b73942f69e80b77fc482686c,

title = "A 152 fsrms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration",

abstract = "This paper introduces an injection-locked phase-locked loop (ILPLL) with multi-phase injection and background self-calibrated. By employing multi-phase injection to enhance injection strength, the noise suppression bandwidth is extended and thus achieving low jitter. Moreover, with injection timing and pulsewidth calibration, the noise suppression bandwidth is further improved, while achieving low spur. The proposed ILPLL is fabricated in a 28-nm CMOS, achieving 152 fs RMS jitter with - 66.5dB cspur and - 247.4dB FoMjitter at 2.4 GHz working frequency. The total power consumption is 7.8 mW from 0.9 V supply voltage.",

keywords = "ILPLL, multi-phase injection, ring oscillator, self-calibrated injection pulse",

author = "Zhen Li and Yuxiao Zhou and Haijin Zhang and Sen Jia and Xing Quan and Xiaodong Zhao and Yuanyuan Cui and Xunying Zhang",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 ; Conference date: 08-09-2025 Through 11-09-2025",

year = "2025",

doi = "10.1109/ESSERC66193.2025.11214107",

language = "英语",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "161--164",

booktitle = "Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025",

}

Li, Z, Zhou, Y, Zhang, H, Jia, S, Quan, X, Zhao, X, Cui, Y & Zhang, X 2025, A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration. 在 Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. European Solid-State Circuits Conference, IEEE Computer Society, 页码 161-164, 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, Munich, 德国, 8/09/25. https://doi.org/10.1109/ESSERC66193.2025.11214107

A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration. / Li, Zhen; Zhou, Yuxiao; Zhang, Haijin 等.
Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. 页码 161-164 (European Solid-State Circuits Conference).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A 152 fsrms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration

AU - Li, Zhen

AU - Zhou, Yuxiao

AU - Zhang, Haijin

AU - Jia, Sen

AU - Quan, Xing

AU - Zhao, Xiaodong

AU - Cui, Yuanyuan

AU - Zhang, Xunying

PY - 2025

Y1 - 2025

N2 - This paper introduces an injection-locked phase-locked loop (ILPLL) with multi-phase injection and background self-calibrated. By employing multi-phase injection to enhance injection strength, the noise suppression bandwidth is extended and thus achieving low jitter. Moreover, with injection timing and pulsewidth calibration, the noise suppression bandwidth is further improved, while achieving low spur. The proposed ILPLL is fabricated in a 28-nm CMOS, achieving 152 fs RMS jitter with - 66.5dB cspur and - 247.4dB FoMjitter at 2.4 GHz working frequency. The total power consumption is 7.8 mW from 0.9 V supply voltage.

AB - This paper introduces an injection-locked phase-locked loop (ILPLL) with multi-phase injection and background self-calibrated. By employing multi-phase injection to enhance injection strength, the noise suppression bandwidth is extended and thus achieving low jitter. Moreover, with injection timing and pulsewidth calibration, the noise suppression bandwidth is further improved, while achieving low spur. The proposed ILPLL is fabricated in a 28-nm CMOS, achieving 152 fs RMS jitter with - 66.5dB cspur and - 247.4dB FoMjitter at 2.4 GHz working frequency. The total power consumption is 7.8 mW from 0.9 V supply voltage.

KW - ILPLL

KW - multi-phase injection

KW - ring oscillator

KW - self-calibrated injection pulse

UR - https://www.scopus.com/pages/publications/105024562404

U2 - 10.1109/ESSERC66193.2025.11214107

DO - 10.1109/ESSERC66193.2025.11214107

M3 - 会议稿件

AN - SCOPUS:105024562404

T3 - European Solid-State Circuits Conference

SP - 161

EP - 164

BT - Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

PB - IEEE Computer Society

T2 - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

Y2 - 8 September 2025 through 11 September 2025

ER -

Li Z, Zhou Y, Zhang H, Jia S, Quan X, Zhao X 等. A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration. 在 Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society. 2025. 页码 161-164. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC66193.2025.11214107

A 152 fsrms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration

摘要

出版系列

会议

访问文件

其它文件与链接

指纹

引用此

A 152 fs_rms Ring-Vco-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration