Zero-Instruction-Storage-Overhead Fault-Tolerant Microarchitecture Based on ISA Redundancy and Address-Correlated Hsiao Code

As embedded processors are increasingly deployed in safety-critical systems, the storage overhead associated with conventional error correction code (ECC) schemes presents a significant challenge for area-sensitive microarchitectures. This article presents a zero-instruction-storage-overhead microarchitecture that achieves robust error protection by leveraging intrinsic architectural redundancies. The proposed methodology leverages the latent structural and alignment redundancies within the instruction set architecture (ISA) to implement an address-correlated Hsiao (AC-Hsiao) encoding scheme. By embedding parity information directly into vacant instruction slots and establishing a mathematical dependence between syndromes and physical fetch addresses, the framework facilitates both memory bit-error correction and instruction-fetch path integrity verification without requiring dedicated check-bit storage. The architecture was implemented and validated on a 28-nm dual-issue SweRV EH1 processor core. The experimental results demonstrate that the design achieves 100% single-error correction and double-error detection (SEC-DED) coverage. Compared to a conventional Hamming-based ECC implementation, the methodology yields a memory reduction of the instruction cache (I-Cache) by 23.53% and the instruction closely-coupled memory (ICCM) by 17.95%, respectively. Relative to the unprotected baseline core, the logic integration incurs a 3.70% area increase and a 2.92% frequency penalty while maintaining native execution efficiency (2.90 DMIPS/MHz and 4.67 CoreMark/MHz). These results substantiate that the proposed strategy effectively offsets minor logic overhead with substantial memory savings and enhanced path-level reliability, providing a viable solution for high-integrity embedded processors.