Abstract
This paper describes the design and implementation of the urgency-based round robin scheduling algorithm based on network processors. The urgency-based round robin algorithm tries to select the most need packets to be served in the multimedia streams or queues. It implements the whole algorithm on Intel IXP2400 network processor and uses some special way such as hierarchical bit vector and urgency index table for performance and finally offers the future research on the algorithm.
| Original language | English |
|---|---|
| Pages (from-to) | 142-144 |
| Number of pages | 3 |
| Journal | Jisuanji Gongcheng/Computer Engineering |
| Volume | 32 |
| Issue number | 4 |
| State | Published - 20 Feb 2006 |
Keywords
- Bit vector
- Microengine
- Network processor
- QoS
- Scheduling algorithm