TY - GEN
T1 - The design and realization of small-sized UAV solid data recorder
AU - Liu, Guanghui
AU - Zhou, Jun
AU - Yu, Xiaozhou
PY - 2011
Y1 - 2011
N2 - According to the application requirements and the design problems of the UAV(Unmanned air vehicle) data recorder, this paper puts forward a solid multi-channel highspeed dynamic airborne data recorder. Based on the design scheme of the data recorder which takes the SOPC(System On Programmable Chip) as the hardware platform and the NAND FLASH as the storage medium, the system can reduce its size and weight effectively while ensure the performance of impact-resistance and data capacity, so that it particularly applies to the minor UAV. Adopting the FPGA hardware logic to implement the multi-channel parallel data acquisition such as pluse data acquisition and serial data acquisition, the system improves the whole system in speed and efficiency. Because of taking the UFFS as the FLASH file system, the memory demands are greatly reduced as well as the startup speed is improved. At the mean time, the accidental data loss caused by power failure is well avoided, so that the reliability and the stability are greatly improved. Through performing tests, the results show that the system can run smoothly and all the demands of the tests are met.
AB - According to the application requirements and the design problems of the UAV(Unmanned air vehicle) data recorder, this paper puts forward a solid multi-channel highspeed dynamic airborne data recorder. Based on the design scheme of the data recorder which takes the SOPC(System On Programmable Chip) as the hardware platform and the NAND FLASH as the storage medium, the system can reduce its size and weight effectively while ensure the performance of impact-resistance and data capacity, so that it particularly applies to the minor UAV. Adopting the FPGA hardware logic to implement the multi-channel parallel data acquisition such as pluse data acquisition and serial data acquisition, the system improves the whole system in speed and efficiency. Because of taking the UFFS as the FLASH file system, the memory demands are greatly reduced as well as the startup speed is improved. At the mean time, the accidental data loss caused by power failure is well avoided, so that the reliability and the stability are greatly improved. Through performing tests, the results show that the system can run smoothly and all the demands of the tests are met.
KW - large file serial transmission
KW - NAND FLASH file system
KW - solid data recorder
KW - SOPC
UR - https://www.scopus.com/pages/publications/80053414121
U2 - 10.1109/EMEIT.2011.6023740
DO - 10.1109/EMEIT.2011.6023740
M3 - 会议稿件
AN - SCOPUS:80053414121
SN - 9781612840857
T3 - Proceedings of 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011
SP - 3086
EP - 3091
BT - Proceedings of 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011
T2 - 2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011
Y2 - 12 August 2011 through 14 August 2011
ER -