Solid-state non-volatile memories based on vdW heterostructure-based vertical-transport ferroelectric field-effect transistors

Driven by the explosive development of data-centric computation applications, it is becoming urgent to develop in-memory computing devices that are beyond the von Neumann architecture with an arrangement of separated logic and memory components. The transistor-type solid-state non-volatile memories, such as ferroelectric field-effect transistors (FeFETs), have long been regarded as a competitive candidate for future in-memory computing architectures. However, the density scaling towards high-density arrays would require advanced FeFETs with reduced footprints, which remains a great challenge so far. Here, a vertical-transport (VT) FeFET that flips the charge transport channel perpendicular to the substrate plane is proposed, in which a ferroelectric gate and a van der Waals (vdW) heterojunction channel are vertically integrated, effectively reducing the device footprints. The proposed VT-FeFET shows not only the robust binary non-volatile memory states but also several key synaptic functionalities at the device level. An artificial neural network with supervised learning was simulated based on the device conductance switching properties, showing excellent classification accuracy for the MNIST handwritten digits. These findings suggest that the proposed VT-FeFET could offer a new solution for future non-volatile memories as well as more advanced neuromorphic systems.