Investigation of Voltage Imbalance in Series-Connected SiC MOSFETs and the Mitigation Method

Voltage imbalance issue in series-connected silicon carbide (SiC) MOSFETs significantly affects the device reliability and lifetime, which are mainly attributed to the different turn-off speeds and drain-source voltage rise rate of series-connected devices caused by the mismatch of control signals, inconsistent parasitic elements, etc. To address the voltage imbalance issue, externally paralleled gate-source capacitance is used to reduce the discrepancy of turn-off speed, while drain-source and drain-gate resistance-capacitance-diode (RCD) circuits are proposed, aiming at a consistent drain-source voltage rise rate of all MOSFETs during switching-off transients. Three 1.2 kV discrete SiC MOSFETs are series-connected to implement a high-voltage pulse switch. The relationship between voltage stress distribution and gate-source capacitance is investigated, and the performance of the proposed RCD circuits is evaluated. Experimental results demonstrate that the MOSFET operating at a slower turn-off speed (larger gate-source capacitance) tends to experience lower voltage stress, vice versa. Furthermore, both drain-source and drain-gate RCD circuits show effectiveness in suppressing the voltage imbalance. In contrast, the drain-gate RCD circuit exhibits higher voltage imbalance suppression and low loss, which achieves 0.53% voltage imbalance rate with R=50Ω and C=5nF when generating 1.6-kV pulses.