Design and implementation of a high performance class D power amplifier controller based on FPGA

Based on the field programmable gate array (FPGA), a 2-channel uniform pulse width modulation (UPWM) controller for high performance class D audio power amplifier systems is designed and implemented. To reduce the consumption of hardware resources, half-band filters, designed as a tapped cascaded interconnection of identical sub-filters, and time division multiplexing for multiplier are employed in the configurable interpolation filter. A look-up table error correction module with low hardware requirements, taking advantage of the high open loop gain of the sigma-delta modulator, is implemented to pre-correct the UPWM nonlinear distortion in baseband. The test results indicate that the controller achieves 114 dB signal-to-noise ratio and -97 dB inter-modulation distortion.