A System Verilog Based Networked Verification and Testing Method for Wireless Network Protocols on Chip

Wireless Network Protocols on Chip (WNPC) is a hardware module with communication networking functions. Aiming at the problem of low WNPC function verification and testing efficiency caused by the complexity and particularity of wireless network environment, a SystemVerilog (SV) based Networked Verification and Testing Method for WNPC is proposed, which can flexibly configure a variety of network application scenarios and node attributes, adapt to a variety of protocols, and test its code and function coverage, as well as network performance such as throughput and average delay. Firstly, the overall architecture of a layer-based networked functional verification and test platform is designed, including five functional modules for single node and network. Secondly, the protocol adaptation module of single-node general WNPC, the wireless channel arbitrator module that can simulate node movement, channel fading, wireless network topology and data exchange, and the design method of simulation result statistics module for network performance are introduced in detail. Then, compared with the traditional single-module test method, the analysis shows the reduction in the number of test vectors in this method. Finally, the simulation results show that the proposed method is not only suitable for multiple network topologies, but also reduces the number of test vectors to be covered by about 45.7% compared with the traditional single-module test.