A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train

Chen Liu, Xizheng Guo, Rui Ma, Zhongliang Li, Franck Gechter, Fei Gao

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

Hardware-in-the-loop (HIL) test provides a time saving and safe environment for testing high-power electronic systems. But the main difficulty for the HIL test of power electronic system lies on the modeling of the complex and high-power system. This paper proposes a modeling method of the electrical system of high-speed train. With this method, the HIL test platform using field-programmable gate array boards is built. Besides, in order to meet the computing power requirement of the system modeling, we simulate the whole system using two dSPACE simulators and inside each dSPACE simulator, a multiprocessor system is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit and auxiliary control unit. The HIL results under steady state and transient conditions demonstrate modeling accuracy and provide a detailed insight into its development.

Original languageEnglish
Article number8444450
Pages (from-to)912-921
Number of pages10
JournalIEEE Transactions on Transportation Electrification
Volume4
Issue number4
DOIs
StatePublished - Dec 2018

Keywords

  • dSPACE simulator
  • field-programmable gate array (FPGA)
  • hardware-in-the-loop (HIL)
  • high-speed train

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