A Fractional-N PLL for Low-Power GNSS Achieving 0.72-ppm/^◦C Frequency Stability and 0.3-dBc/Hz Phase Noise Variation From −40 ^◦C to 125 ^◦C

Driven by the stringent demands of Internet of Things (IoT) applications, extended battery life and robust temperature stability have become key design metrics for navigation and positioning chips. This article presents a low-power fractional-N phase-locked loop (PLL) with temperature compensation for navigation and positioning applications. The proposed PLL integrates a temperature-adaptive dual-loop Class-C voltage-controlled oscillator (VCO). Benefiting from the high current efficiency and reduced temperature sensitivity of the proposed dual-loop VCO, the PLL simultaneously achieves low-power consumption, stable frequency generation, and low-phase noise (PN) over a wide temperature range. Fabricated in a 0.13-µm CMOS process, the PLL consumes 5.6 mW from a 1.2 V supply. Measurement results over a temperature range of −40 ^◦C to 125 ^◦C demonstrate that the proposed PLL achieves an average frequency temperature coefficient (TC) of 0.72 ppm/^◦C. In addition, the PN variation remains below 0.3 dBc/Hz at a 100-kHz offset and 0.8 dBc/Hz at a 1-MHz offset.