A 48-dB Range, 0.86-dB Step, and 0.06-dB Error dB-Linear PGA Based on Resistive Ladder Attenuator: Design Theory and Realization

This paper presents the effective design theory and realization for a programmable gain amplifier (PGA) with extremely small gain error and high-resolution decibel (dB)-linear characteristic in a 48 dB gain control range. Based on the resistive ladder attenuator topology and the complementary binary-weighted switching technique, the gain error in digitally controlled dB-linear characteristic is significantly reduced by introducing an optimization factor in the pseudo-exponential function fitting. To achieve both extremely small gain error and a relatively wide gain range, an optimization method for trading off different types of gain error is employed to obtain the optimal optimization factor. An adaptive bias circuit is adopted to realize gain robustness to process and temperature variations.The proposed PGA is fabricated in a 0.18 $\mu$ m CMOS technology with a 0.063 $^{2}$ core area. The power consumption is 5.3 mW at a supply voltage of 1.8 V. It provides a dB-linear gain range from -20 dB to 28 dB with a 0.86 dB gain step while the gain error is less than 0.06 dB. The PGA exhibits a -3 dB bandwidth of 80 MHz in various digital control words. The measured input 1-dB compression point is from -27.7 to 13 dBm, and the noise figure is from 13.4 to 62.5 dB.