Abstract
A novel circuit architecture for programmable gain amplifier (PGA) is proposed, which simplifies and improves the conventional one and achieves wide precise digital decibel (dB)-linear gain control while obtaining a smaller gain error, smaller chip area and wider bandwidth with low power consumption. In the 0.18-μm CMOS process, the proposed PGA occupies less than 0.09mm2 of chip area. From the measurements, the PGA shows a dB-linear gain range of 48 dB (−20 to 28 dB) with a gain error of less than 0.18 dB, a gain step of 0.86 dB, a maximum 1-dB compression point (IP1dB) of 10.4 dBm, and a 3-dB bandwidth of 450MHz at the maximum gain while consuming only 5.8mA from a 1.8-V supply.
| Original language | English |
|---|---|
| Article number | 20140940 |
| Pages (from-to) | 1-6 |
| Number of pages | 6 |
| Journal | IEICE Electronics Express |
| Volume | 11 |
| Issue number | 21 |
| DOIs | |
| State | Published - 17 Oct 2014 |
| Externally published | Yes |
Keywords
- Decibel (dB)-linear gain
- GNSS receiver chip
- Programmable gain amplifier (PGA)
- Variable gain amplifier (VGA)
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