A - 247.4dB Jitter-FoM Ring-VCO-based SSPLL with Discrete-Time Phase Noise Cancellation and Adaptive Gain Mismatch Adjustment

With the rapid growth of communication data rates, increasingly stringent jitter performance requirements are imposed on clock signals. Clock generators incorporating ring-VCO (RVCO) based phase-locked loops (PLLs) have garnered significant attention due to their numerous advantages, including wide tuning range, compact chip area, and the capability to generate multi-phase output. However, the inherently poor phase noise of RVCOs has emerged as a bottleneck of RVCO PLLs. The injection-locked technique can effectively suppress the phase noise in RVCOs by aligning phase cycles to eliminate accumulated jitter [1-3]. However, it requires complex calibration to avoid performance degradation due to process, voltage, and temperature (PVT), as depicted in Fig. 1 (top-left). Phase noise cancellation (PNC) technology is another solution to reduce the jitter contributed by RVCOs [4-8]. [4] proposes a subsampling phase-locked loop (SSPLL) with feedforward PNC (FPNC) technology. It extracts noise through the sub-sampling phase detector (SSPD) and cancels it in feed-forward path outside SSPLL loop, significantly suppressing the phase noise of RVCO without affecting SSPLL loop, as shown in Fig. 1 (top-right). However, the noise cancellation block (NCB) limits the power consumption and operating frequency of the SSPLL, and the gain of the NCB needs to be manually calibrated. Fig. 1 (bottom-left) illustrates a calibration-free SSPLL with open-loop discrete-time phase-noise cancellation [5]. Although the issue of manual calibration has been resolved, it still faces power consumption limitation of NCB in high frequency.